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1

A24: Hardware acceleration of sorting algorithms using reconfiguration technics

Russek, Paweł, Wiatr, Kazimierz

Journal:

IFAC Proceedings Volumes

Year:

2004

Language:

english

File:

PDF, 138 KB

english, 2004

2

The prospect of computing acceleration using reconfigurable logic technology in huge computation power systems

Russek, Pawel, Wiatr, Kazimierz

Journal:

IFAC Proceedings Volumes

Year:

2006

Language:

english

File:

PDF, 6.63 MB

english, 2006

3

[IEEE 2018 International Conference on Signals and Electronic Systems (ICSES) - Kraków, Poland (2018.9.10-2018.9.12)] 2018 International Conference on Signals and Electronic Systems (ICSES) - Analog to Digital Converter with FPGA Interface and Measurements for Custom Base Station Transceiver

Gajoch, Grzegorz, Zapart, Mateusz, Macheta, Jan, Worek, Cezary, Russek, Pawel

Year:

2018

Language:

english

File:

PDF, 1.89 MB

english, 2018

4

[IEEE 2008 International Conference on Signals and Electronic Systems - Krakow, Poland (2008.09.14-2008.09.17)] 2008 International Conference on Signals and Electronic Systems - AES hardware implementation in FPGA for algorithm acceleration purpose

Gielata, Artur, Russek, Pawel, Wiatr, Kazimierz

Year:

2008

Language:

english

File:

PDF, 93 KB

english, 2008

5

A study of the loops control for reconfigurable computing with OpenCL in the LABS local search problem

Russek, Paweł, Jamro, Ernest, Dąbrowska-Boruch, Agnieszka, Wiatr, Kazimierz

Journal:

International Journal of High Performance Computing Applications

Year:

2019

File:

PDF, 1.44 MB

2019

6

Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration

Pietroń, Marcin, Russek, Paweł, Wiatr, Kazimierz

Journal:

International Journal of Applied Mathematics and Computer Science

Year:

2010

Language:

english

File:

PDF, 244 KB

english, 2010

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